Magnetoresistive random access memory (MRAM) is a type of memory device containing an array of MRAM cells that store data using their resistance values instead of electronic charges. Generally, each MRAM cell includes a magnetic tunnel junction (MTJ) structure. The MTJ structure may have adjustable resistance to represent a logic state “0” or “1.” The MTJ structure typically includes a stack of magnetic layers having a configuration in which two ferromagnetic layers are separated by a thin non-magnetic dielectric, e.g., an insulating tunneling layer. A top electrode and a bottom electrode are utilized to sandwich the MTJ structure so electric current may flow between the top and the bottom electrode.
One ferromagnetic layer, e.g., a reference layer, is characterized by a magnetization with a fixed direction. The other ferromagnetic layer, e.g., a storage layer, is characterized by a magnetization with a direction that is varied upon writing of the device, such as by applying a magnetic field. In some devices, an insulator material, such as a dielectric oxide layer, may be formed as a thin tunneling barrier layer sandwiched between the ferromagnetic layers. The layers are typically deposited sequentially as overlying blanketed films. The ferromagnetic layers and the insulator material are subsequently patterned by various etching processes in which one or more layers are removed, either partially or totally, in order to form a device feature.
When the respective magnetizations of the reference layer and the storage layer are antiparallel, a resistance of the magnetic tunnel junction is high having a resistance value Rmax corresponding to a high logic state “1”. On the other hand, when the respective magnetizations are parallel, the resistance of the magnetic tunnel junction is low, namely having a resistance value Rmin corresponding to a low logic state “0”. A logic state of a MRAM cell is read by comparing its resistance value to a reference resistance value Rref, which is derived from a reference cell or a group of reference cells and represents an in-between resistance value between that of the high logic state “1” and the low logic state “0”.
Spin-transfer-torque magnetic random access memory (STT MRAM) and spin-orbit-torque magnetic random access memory (SOT MRAM) are different chip architectures that each has its own electrical performance and energy efficiency. Spin-orbit-torque magnetic random access memory (SOT MRAM) has been wildly studied for MRAM applications. However, external or internal generated magnetic field is also required when operating the spin-orbit-torque magnetic random access memory (SOT MRAM). However, such requirement often complicates the manufacturing process as well as increasing the manufacturing cost. Thus, how to fabricate spin-orbit-torque magnetic random access memory (SOT MRAM) with relatively simple structure as well as low manufacturing cost remains a challenge.
Therefore, there is a need in the art for improved methods and apparatus for fabricating MTJ structures for MRAM applications.